1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a highly integrated semiconductor memory device having a capacitor over bit-line (COB) cell structure, and to a method for manufacturing the same.
2. Description of the Related Art
As semiconductor memory devices such as dynamic random access memories (DRAMs) become more highly integrated, it is very important to develop a process for increasing their cell capacitance and securing a process margin for forming a fine metal interconnection. In general, a surface step is formed between a cell array region, where a storage electrode is formed, and a peripheral circuit region for driving the cells. In the process of forming these metal interconnections on a substrate where the surface step is formed, a technology for uniformly forming a metal interconnection in the cell array region and the peripheral circuit region is very important.
In particular, in highly integrated 256 M-bit DRAMs and above, the height of the storage electrode of the capacitor is increased to 1 .mu.m in order to secure cell capacitance. At this time, a step generated between the cell array region and the peripheral circuit region is also formed at a height of 1 .mu.m. Thus, it is very difficult to uniformly form a metal interconnection over the cell region and the peripheral circuit region even after a subsequent process of planarization.
FIG. 1 is a sectional view of a conventional DRAM device.
Referring to FIG. 1, reference numeral 10 denotes a semiconductor substrate; reference numeral 12 denotes a word line acting as a gate electrode of an access transistor formed in a cell array region; reference numeral 13 denotes a first interdielectric layer covering the access transistor; reference numeral 14 denotes a bit line connected to a source region (or drain region) of the access transistor; reference numeral 16 denotes a second interdielectric layer covering the surface of the resultant structure where the bit line 14 is formed; reference character Cl denotes a storage electrode connected to the drain region (or source region) of the access transistor; reference character C2 denotes a plate electrode covering the cell array region of the resultant structure where the storage electrode C1 is formed; reference numeral 18 denotes a third interdielectric layer covering a cell array region and a peripheral circuit region of the resultant structure where the plate electrode C2 is formed; and reference numeral 20 denotes a metal interconnection formed on the third inter dielectric layer 18.
As described above, in the conventional memory device, a COB structure is widely used to obtain sufficient cell capacitance. That is, in order to form a high performance capacitor, a COB structure where a three-dimensional cell capacitor is formed on a semiconductor substrate over a bit line, is widely employed in DRAM devices. However, although increasing the height of the storage electrode formed in a restricted unit cell area allows the desired cell capacitance to be obtained, it also increases a step "h" between the cell array region and the peripheral circuit region, as shown in FIG. 1. Thus, if photoresist is coated on the third interdielectric layer by a spin coating method, there is a large difference in the thickness of the photoresist layer between the cell array region and a peripheral circuit region. This reduces a focus margin during a photo-lithography process, and a photoresist pattern having abnormal profile is formed in the cell array region and the peripheral circuit region. Accordingly, it is difficult to normally etch using the photoresist pattern as an etching mask, because the photoresist pattern has an abnormal profile.
In order to reduce the step between the cell array region and the peripheral circuit region, there is a method for excessively planarizing the third interdielectric layer. However, in this case the depth of a metal contact hole formed by etching the first through third interdielectric layers is increased. As a result, it is more difficult to improve the reliability of the metal interconnection filling the metal contact hole.